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CXP86541/86549/86561
CMOS 8-bit Single Chip Microcomputer
Description The CXP86541/86549/86561 are the CMOS 8-bit microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time-base timer, on-screen display function, I2C bus interface, PWM output, remote control reception circuit, HSYNC counter, watchdog timer, 32kHz timer/counter besides the basic configurations of 8-bit CPU, ROM, RAM, I/O ports. The CXP86541/86549/86561 also provide a sleep function that enables to lower the power consumption. 52 pin SDIP (Plastic)
Features Structure * A wide instruction set (213 instructions) which Silicon gate CMOS IC covers various types of data - 16-bit operation/multiplication and division/ Boolean bit operation instructions * Minimum instruction cycle 250ns at 16MHz operation (4.5 to 5.5V) 122s at 32kHz operation (2.7 to 5.5V) * Incorporated ROM 40K bytes (CXP86541) 48K bytes (CXP86549) 60K bytes (CXP86561) * Incorporated RAM 1536 bytes (Excludes VRAM for on-screen display and sprite RAM) * Peripheral functions - A/D converter 8-bit 6-channel successive approximation method (Conversion time of 3.25s at 16 MHz) - Serial interface 8-bit clock sync type, 1 channel - Timer 8-bit timer 8-bit timer/counter 19-bit time-base timer 32kHz timer/counter - On-screen display (OSD) function 12 x 16 dots, 512 character types, 15 character colors, 2 lines x 24 characters, frame background 8 colors/ half blanking, background on full screen 15 colors/ half blanking edging/ shadowing/ rounding for every line, background with shadow for every character, double scanning, sprite OSD, 12 x 16 dots, 1 screen, 8 colors for every dot - I2C bus interface - PWM output 8 bits, 6 channels 14 bits, 1 channel - Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO - HSYNC counter 2 channels - Watchdog timer * Interruption 13 factors, 13 vectors, multi-interruption possible * Standby mode Sleep * Package 52-pin plastic SDIP * Piggyback/evaluator CXP86490 64-pin ceramic PSDIP (Supports custom font)
Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E96Z15A86
INT0 INT1 INT2
RMC
REMOCON
FIFO
SI SO SCK 2
SERIAL INTERFACE UNIT
INTERRUPT CONTROLLER
PORT B
ROM 12K/16K/24K/32K/ 40K/48K/60K BYTES RAM 352/704/1536 BYTES 8
PORT A
AN0 to AN5 8
6
A/D CONVERTER 6CH
SPC700 CPU CORE
TEX TX EXTAL XTAL RST MP VDD VSS
CLOCK GENERATOR /SYSTEM CONTROL PA0 to PA7
Block Diagram
PB0 to PB7
TO
8BIT TIMER 1 2 PE0 to PE1
PORT E
XLC EXLC R G B I YS YM HSYNC VSYNC 2 PRESCALER/ TIME BASE TIMER WATCHDOG TIMER 32kHz TIMER/COUNTER
PORT D
EC
8BIT TIMER/ COUNTER 0
8
PD0 to PD7
PORT F
2 I2C BUS INTERFACE UNIT 8BIT PWM 6 14BIT PWM
HS1
HSYNC COUNTER 1
ADJ
SDA0
SDA1
SCL0
SCL1
PWM0 to PWM5
PWM
PORT G
-2-
2 3
PE2 to PE3 PE4 to PE6
ON SCREEN DISPLAY
8
PF0 to PF7
HS0
HSYNC COUNTER 0
1
PG7
CXP86541/86549/86561
CXP86541/86549/86561
Pin Assignment (Top View)
EC/PD7 RMC/PD6 HS1/PD5 HS0/PD4 SI/PD3 SO/PD2 SCK/PD1 INT2/PD0 HSYNC/PA7 VSYNC/PA6 RST VSS XTAL EXTAL PA5/AN5 PA4/AN4 PA3/AN3 PA2/AN2 PA1/AN1 PA0/AN0 PB7 PB6 PB5 PB4 PB3 INT1/PG7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
PF0/PWM0 PF1/PWM1 PF2/PWM2 PF3/PWM3 PF4/SCL0 PF5/SCL1/PWM4 PF6/SDA0 PF7/SDA1/PWM5 PE0/TO/ADJ PE1/PWM PE2/TEX/INT0 PE3/TX VSS VDD NC EXLC XLC PE4/YM PE5/YS PE6/I B G R PB0 PB1 PB2
Note) 1. NC (Pin 38) is left open. 2. Vss (Pins 12 and 40) are both connected to GND.
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CXP86541/86549/86561
Pin Description Symbol PA0/AN0 to PA5/AN5 PA6/VSYNC PA7/HSYNC PB0 to PB7 I/O I/O/ Analog input I/O/Input I/O/Input I/O (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) Description Analog inputs to A/D converter. (6 pins) OSD display vertical sync signal input. OSD display horizontal sync signal input.
(Port B) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) External interruption request input. Active at the falling edge. (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Can drive 12mA synk current. (8 pins) Serial clock I/O. Serial data output. Serial data input. HSYNC counter (CH0) input. HSYNC counter (CH1) input. Remote control reception circuit input. External event input for timer/counter. Rectangular wave output for 8-bit timer/counter. (Port E) Bits 0 and 1 are I/O port; I/O can be set in a unit of single bits. Bits 2 and 3 are for input. Bits 4, 5 and 6 are for output. (7 pins) 14-bit PWM output. External interruption Connects a crystal for request input. Active at 32kHz timer/counter the falling edge. clock oscillation. When used as an event counter, input to TEX pin and leave TX pin open. 32kHz oscillation frequency dividing output.
PD0/INT2 PD1/SCK PD2/SO PD3/SI PD4/HS0 PD5/HS1 PD6/RMC PD7/EC PE0/TO/ADJ PE1/PWM PE2/TEX/INT0
I/O/Input I/O/I/O I/O/Output I/O/Input I/O/Input I/O/Input I/O/Input I/O/Input I/O/Output/ Output I/O/Output Input/Input/ Input Input/Output Output/Output Output/Output Output/Output Output Output Output
PE3/TX PE4/YM PE5/YS PE6/I B G R
OSD display 6-bit output. (6 pins)
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CXP86541/86549/86561
Symbol PF0/PWM0 to PF3/PWM3 PF4/SCL0 PF5/SCL1/ PWM4 PF6/SDA0 PF7/SDA1/ PWM5 PG7/INT1 EXTAL XTAL RST EXLC XLC NC VDD Vss
I/O Output/Output Output/I/O Output/I/O/ Output Output/I/O Output/I/O/ Output I/O/Input Input Output Input Input Output (Port F) 8-bit output port and large current (12mA) N-channel open drain output. Lower 4 bits are midium drive voltage (12V); upper 4 bits are 5V drive. (8 pins) (Port G) 1-bit I/O port.
Description 8-bit PWM output. (4 pins) I2C bus interface transfer clock I/O. (2 pins) 8-bit PWM output. I2C bus interface transfer data I/O. (2 pins) 8-bit PWM output. External interruption request input. Active at the falling edge.
Connects a crystal for system clock oscillation. When a clock is supplied externally, input it to EXTAL pin and input a reversed phase clock to XTAL pin. System reset; active at Low level. OSD display clock oscillation I/O. Oscillation frequency is determined by the external L and C. No connected. Positive power supply. GND. Connect two Vss pins to GND.
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CXP86541/86549/86561
Input/Output Circuit Formats for Pins Pin Port A
Port A data Port A direction
Circuit format
When reset
PA0/AN0 to PA5/AN5
"0" when reset IP RD (Port A) Port A function selection "0" when reset A/D converter Input multiplexer Input protection circuit
Data bus
Hi-Z
6 pins Port A
Port A data Port A direction
PA6/VSYNC PA7/HSYNC
Data bus RD (Port A) HSYNC, VSYNC
"0" when reset Schmitt input
IP
Hi-Z
Input polarity "0" when reset
2 pins Port B Port G PB0 to PB7 PG7/INT1
Data bus RD (Ports B, G) Ports B, G data Ports B, G direction "0" when reset
Schmitt input for PB0, PB1, PB2, PG7
Hi-Z
IP
9 pins Port F
INT1
PWM0 to PWM3
PF0/PWM0 to PF3/PWM3
Port F function selection "0" when reset Port F data "1" when reset 12V drive voltage Large current 12mA
Hi-Z
4 pins -6-
CXP86541/86549/86561
Pin Port D
Circuit format
When reset
Port D data
PD0/INT2 PD3/SI PD4/HS0 PD5/HS1 PD6/RMC PD7/EC
Port D direction "0" when reset Schmitt input RD (Port D) INT2, SI, HS0, HS1, RMC, EC Large current 12mA
Hi-Z
Data bus IP
6 pins
Port D
SCK, SO SIO output enable
Port D data
PD1/SCK PD2/SO
Port D direction "0" when reset Data bus RD (Port D) Schmitt input only for PD1
Hi-Z
IP
2 pins Port E
SCK only
Large current 12mA
Internal reset signal Port E data "1" when reset TO ADJ16K1 ADJ2K1 00 01 10 11 MPX 2
PE0/TO/ADJ
Port E function selection (Upper) Port E function selection (Lower)
"00" when reset Port E direction "1" when reset Data bus
1 ADJ signals are frequency dividing outputs for 32kHz oscillation frequency IP adjustment. ADJ2K provides usage as buzzer output. 2 Pull-up resistors approx. 150k
High level (with approximately 150k resistor when reset)
1 pin
RD (Port E)
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CXP86541/86549/86561
Pin Port E
Circuit format
When reset
PWM Port E function selection "0" when reset Port E data
PE1/PWM
"1" when reset
High level
Port E direction "1" when reset IP Data bus
1 pin Port E
RD (Port E)
32kHz oscillation circuit control "1" when reset Schmitt input INT0 Data bus
PE2/TEX/INT0 PE3/TX
PE2/ TEX/ INT0 IP IP
RD (Port E) Data bus RD (Port E) Schmitt input Clock input
Oscillation halted Port input
2 pins
PE3/ TX
Port E
YM, YS, I Output polarity
PE4/YM PE5/YS PE6/I
"0" when reset Port E function selection "0" when reset Port E data Writing data to output polarity register and port data register brings output to active.
Hi-Z
3 pins
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CXP86541/86549/86561
Pin Port F
SCL, SDA I2C bus enable
Circuit format
When reset
PF4/SCL0 PF5/SCL1/PWM4 PF6/SDA0 PF7/SDA1/PWM5
PWM4, PWM5 Port F function selection "0" when reset Port F data "1" when reset SCL, SDA (I2C bus circuit) Schmitt input IP BUS SW
Hi-Z
4 pins
Large current 12mA
To internal pins (SCL1 for SCL0)
I 2C
R, G, B
R G B
Output polarity "0" when reset
Hi-Z
Writing data to output polarity register brings output to active.
3 pins
Oscillation control
EXLC XLC
EXLC
IP
IP
OSD display clock
Oscillation halted
XLC
2 pins
EXTAL XTAL
EXTAL
IP * Diagram shows the circuit composition during oscillation. * Feedback resistor is removed during stop mode. (This device does not enter stop mode.)
Oscillation
2 pins
XTAL
Pull-up resistor
RST
OP Mask option Schmitt input
Low level
1 pin
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CXP86541/86549/86561
Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Symbol VDD VIN VOUT Ratings -0.3 to +7.0 -0.3 to +7.01 -0.3 to +7.01 -0.3 to +15.0 -5 -50 15 20 130 -20 to +75 -55 to +150 375 Unit V V V V mA mA mA mA mA C C mW SDIP-52P-01
(Vss = 0V reference) Remarks
Mid-voltage drive output voltage VOUTP High level output current High level total output current IOH IOH IOL Low level output current IOLC Low level total output current Operating temperature Storage temperature Allowable power dissipation IOL Topr Tstg PD
Total of all output pins Ports excluding large current output (value per pin) Large current output ports (value per pin2) Total of all output pins
1 VIN and VOUT should not exceed VDD + 0.3V. 2 The large current output port is Port D (PD) and Port F (PF). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. Recommended Operating Conditions Item Symbol Min. 4.5 VDD 3.5 2.7 -- VIH High level input voltage VIHS VIHEX VIL Low level input voltage VILS VILEX Operating temperature Topr 1 2 3 4 5 0.7VDD 0.8VDD Max. 5.5 5.5 5.5 -- VDD VDD Unit V V V V V V V V V V C (Vss = 0V reference) Remarks Guaranteed operation range for 1/2 and 1/4 frequency dividing modes Guaranteed operation range for 1/16 frequency dividing mode or sleep mode Guaranteed operation range for TEX mode Guaranteed data hold range for stop mode5 1 2 EXTAL pin3, TEX pin4 1 2 EXTAL pin3, TEX pin4
Supply voltage
VDD - 0.4 VDD + 0.3 0 0 -0.3 -20 0.3VDD 0.2VDD 0.4 +75
PA1 to PA5, PB3 to PB7, PD2, PE0, PE1, PE3, SCL0, SCL1, SDA0, SDA1 pins VSYNC, HSYNC, INT2, SCK, SI, HS0, HS1, RMC, EC, INT0, INT1, RST, PB0, PB1, PB2 pins Specifies only during external clock input. Specifies only during external event count input. This device does not enter the stop mode. - 10 -
CXP86541/86549/86561
Electrical Characteristics DC characteristics Item High level output voltage Symbol Pins PA, PB, PD, PE0 to PE1, PE4 to PE6, PG7, R, G, B (Ta = -20 to +75C, Vss = 0V reference) Conditions VDD = 4.5V, IOH = -0.5mA VDD = 4.5V, IOH = -1.2mA Min. 4.0 3.5 0.4 0.6 1.5 0.4 0.6 0.5 -0.5 0.1 -0.1 -1.5 40 -40 10 -10 -400 10 50 10 120 Typ. Max. Unit V V V V V V V A A A A A A A A
VOH
PA, PB, PD, PE0 to PE1, VDD = 4.5V, IOL = 1.8mA PE4 to PE6, PF0 to PF3, VDD = 4.5V, IOL = 3.6mA PG7, R, G, B Low level output voltage VOL PD, PF PF4 to PF7 (SCL0, SCL1, SDA0, SDA1) IIHE IILE Input current IIHT IILT IILR I/O leakage current Open drain I/O leakage current (in N-ch Tr off state) I2C bus switch connection impedance (in output Tr off state) IIZ EXTAL VDD = 4.5V, IOL = 12.0mA VDD = 4.5V, IOL = 3.0mA VDD = 4.5V, IOL = 4.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V
TEX RST1
VDD = 5.5V, PA, PB, PD, PE, PG7, R, G, B, RST1 VI = 0, 5.5V PF0 to PF3 VDD = 5.5V, VOH = 12.0V VDD = 5.5V, VOH = 5.5V VDD = 4.5V VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V 1/2 frequency dividing mode
ILOH PF4 to PF7 RBS SCL0: SCL1 SDA0: SDA1
IDD1
VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3.3V, 32MHz crystal oscillation (C1 = C2 = 47pF) SLEEP mode
18
28
mA
IDD2
30
80
A
Supply current2
IDDS1
VDD
VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3.3V, 32MHz crystal oscillation (C1 = C2 = 47pF) STOP mode3 VDD = 5.5V, termination of 16MHz and 32MHz oscillation --
1.2
2.1
mA
IDDS2
12
35
A
IDDS3
--
--
A
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CXP86541/86549/86561
Item
Symbol
Pins PA, PB, PD,PE0 to PE3, R, G, B, PF4 to PF7 ,PG7 ,EXTAL, TEX, EXLC, RST
Conditions Clock 1 MHz 0V other than the measured pins
Min.
Typ.
Max.
Unit
Input capacitance
CIN
10
20
pF
1 For RST pin, specifies the input current when pull-up resistance is selected, and specifies the leakage current when non-resistor is selected. 2 When all output pins are left open. Specifies only when the OSD oscillation is halted. 3 This device does not enter the stop mode.
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CXP86541/86549/86561
AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise and fall times Event count input clock pulse width Event count input clock rise and fall times System clock frequency Event count input clock pulse width Event count input clock rise and fall times Symbol fC Pins XTAL EXTAL EXTAL EXTAL EC EC TEX TX TEX TEX (Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Fig. 1, Fig.2 Fig. 1, Fig.2 External clock drive Fig. 1, Fig.2 External clock drive Fig. 3 Fig. 3 VDD = 2.7 to 5.5 V Fig. 2 (32kHz clock applied conditions) Fig. 3 Fig. 3 10 20 4tsys1 20 Min. 8 28 200 Typ. Max 16 Unit MHz ns ns ns ms
tXL, tXH tCR, tCF tEH, tEL tER, tEF
fC
32.768
kHz
tTL, tTH tTR, tTF
s ms
1 Indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits (CPU clock selection). tsys (ns) = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Fig. 1. Clock timing
1/fc
VDD - 0.4V EXTAL 0.4V tXH tCF tXL tCR
Fig.2. Clock applied conditions
Crystal oscillation Ceramic oscillation External clock 32kHz clock applied condition Crystal oscillation
EXTAL C1
XTAL C2
EXTAL
XTAL
TEX
TX
74HC04
C1
C2
Fig. 3. Event count clock timing
TEX EC 0.8VDD 0.2VDD tEH tTH tEF tTF tEL tTL tER tTR
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CXP86541/86549/86561
(2) Serial transfer Item SCK cycle time SCK High and Low level widths SI input setup time (for SCK ) SI hold time (for SCK ) SCK SO delay time Symbol Pins SCK
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Input mode Output mode SCK SCK input mode SCK output mode SI SCK input mode SCK output mode SI SCK input mode SCK output mode SO SCK input mode SCK output mode Min. 1000 8000/fc 400 4000/fc - 50 100 200 200 100 200 100 Max. Unit ns ns ns ns ns ns ns ns ns ns
tKCY tKH tKL tSIK tKSI tKSO
Note) The load of SCK output mode and SO output delay time is 50pF + 1TTL.
Fig. 4. Serial transfer timing
tKCY tKL tKH
0.8VDD SCK 0.2VDD
tSIK
tKSI
0.8VDD SI Input data 0.2VDD
tKSO
0.8VDD SO 0.2VDD Output data
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CXP86541/86549/86561
(3) A/D converter Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Analog input voltage VZT1 VFT2 Symbol Pins
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Min. Typ. Max. 8 3 Ta = 25C VDD = 5.0V Vss = 0V -10 4910 26/fADC3 6/fADC3 AN0 to AN5 0 VDD 10 4970 70 5030 Unit Bits LSB mV mV s s V
tCONV tSAMP
VIAN
Fig. 5. Definitions for A/D converter terms
FFh FEh
Digital conversion value
Linearity error
1 VZT: Value at which the digital conversion value changes from 00h to 01h and vice versa. 2 VFT: Value at which the digital conversion value changes from FEh to FFhand vice versa. 3 fADC indicates the below values due to the contents of bit 6 (CKS) of the A/D control register (ADC: 00F6h): fADC = fc (CKS = "0"), fc/2 (CKS = "1")
01h 00h
VZT Analog input
VFT
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CXP86541/86549/86561
(4) Interruption, reset input (Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item External interruption High, Low level widths Reset input Low level width Symbol Pins INT0 INT1 INT2 RST Conditions Min. 1 32/fc Max. Unit s s
tIH tIL tRSL
Fig. 6. Interruption input timing
tIH INT0 INT1 INT2 (falling edge) tIL
0.8VDD 0.2VDD
Fig. 7. RST input timing
tRSL
RST 0.2VDD
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CXP86541/86549/86561
(5) I2C bus timing Item SCL clock frequency Bus-free time before starting transfer Hold time for starting transfer Clock Low level width Clock High level width Setup time for repeated transfers Data hold time Data setup time SDA, SCL rise time SDA, SCL fall time Setup time for transfer completion Symbol fSLC
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Pins SCL SDA, SCL SDA, SCL SCL SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL 4.7 Conditions Min. 0 4.7 4.0 4.7 4.0 4.7 01 250 1 300 Max. 100 Unit kHz s s s s s s ns s ns s
tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO
1 The data hold time should be 300ns or more because the SCL rise time (300ns Max.) is not included in it.
Fig. 8. I2C bus transfer timing
SDA tBUF tR tF tHD; STA
SCL tHD; STA tSU; STA P S tLOW tHD; DAT tHIGH tSU; DAT St tSU; STO P
Fig. 9. I2C bus device recommended circuit
I2C bus device RS SDA0 (or SDA1) SCL0 (or SCL1) RS RS
I2C bus device RS RP RP
* A pull-up resistor (Rp) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1). * The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance can be used to reduce the spike noise caused by CRT flashover.
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CXP86541/86549/86561
(6) OSD timing Item OSD clock frequency HSYNC pulse width VSYNC pulse width HSYNC afterwrite rise and fall times VSYNC beforewrite rise and fall times
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol fOSC Pins EXLC XLC HSYNC VSYNC HSYNC VSYNC Conditions Fig. 11 Fig. 10 Fig. 10 Fig. 10 Fig. 10 Min. 4 2 1 200 1.0 Max 281 Unit MHz s H2 ns s
tHWD tVWD tHCG tVCG
1 The maximum value of fosc is specified with the following equation. fosc [max] fc x 1.9 2 H indicates 1HSYNC period.
Fig. 10. OSD timing
tHCG
tHWD
HSYNC For OSD I/O polarity register (OPOL: 01FEh) bit 7 at "0"
0.8VDD
0.2VDD
tVCG
tVWD
VSYNC For OSD I/O polarity register (OPOL: 01FEh) bit 6 at "0"
0.8VDD
0.2VDD
Fig. 11. LC oscillation circuit connection
EXLC
XLC R1 L
C1
C2
1 The series resistor for XLC is used to reduce the frequency of occurrence of the undesired radiation.
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CXP86541/86549/86561
Appendix Fig. 12. Recommended oscillation circuit
(i) Main clock (ii) Main clock (iii) Sub clock
EXTAL
XTAL Rd
EXTAL
XTAL Rd C1
TEX
TX Rd C2
C1
C2 C1 C2
Manufacture
Model CSA10.0MTZ CSA12.0MTZ
fc (MHz) 10.0 12.0 16.0 10.0 12.0 16.0 8.0
C1 (pF) 30 5 30 5 18 12 10 10 5 Open 30
C2 (pF) 30
Rd ()
Circuit example
(i) 5 30 5 18 12 10 10 5 Open 33 120k (iii) 0 1 330 1 (i) 0 1 (ii)
MURATA MFG CO., LTD.
CSA16.00MXZ040 CST10.0MTW CST12.0MTW CST16.00MXW0C1
RIVER ELETEC CO., LTD.
HC-49/U03
12.0 16.0 8.0
HC-49/U (-S) KINSEKI LTD. P3
12.0 16.0 32.768kHz
Models with an astarisk have the built-in ground capacitance (C1, C2). 1 The series resistor for XTAL (Rd = 500 or less) can reduce the effect of the noise caused by the electrostatic discharge.
Mask Option Table Item Reset pin pull-up resistor Non-existent Content Existent
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CXP86541/86549/86561
Fig. 13. Characteristic curve
IDD vs. VDD
(fc = 16MHz, Ta = 25C, Typical) 100
IDD vs. fc
(VDD = 5V, Ta = 25C, Typical)
1/2 dividing mode 10 1/4 dividing mode 15 1/2 dividing mode 1/16 dividing mode
IDD - Supply current [mA]
1
Sleep mode
IDD - Supply current [mA]
10 1/4 dividing mode
0.1 32kHz operation mode 32kHz sleep mode 0.01 Sleep mode 1 2 3 6 7 4 5 VDD - Supply voltage [mA] 0 0 5 10 Frequency [MHz] 15 5 1/16 dividing mode
Parameter curve for OSD oscillator L vs. C
(Analytically calculated value) 100
10
L - Inductance [H]
16MHz 1 20MHz 24MHz 28MHz 30MHz
fOSC = 0.1
1 2 LC
C = C1//C2
0.01 0
10
20
30
40
50
60
70
80
90 100
C1, C2 - Capacitance [pF]
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CXP86541/86549/86561
Package Outline
Unit: mm
52PIN SDIP (PLASTIC) 600mil
+ 0.4 47.0 - 0.1 52 27
+ 0.3 13.5 - 0.1
+ 0.1 .05 0.25 - 0
26 1.778
1
15.24
0 to 15
0.5 0.1 + 0.1 0.9 - 0.05
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SDIP-52P-01 SDIP052-P-0600-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER
- 21 -
2.8 MIN
0.51 MIN
5.0 MIN

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